1. Field of the Invention
The invention relates to the field of electronic storage devices, particularly to interleave techniques for accessing digital memory circuits.
2. Description of Background Art
Conventional computer and electronic systems store and retrieve digital data in memory circuits, typically provided in semiconductor chips as dynamic random access memories (DRAMs). To improve system performance, various techniques are known for reducing time to access storage locations in digital memory. For example, U.S. Pat. Nos. 5,051,889, and 4,924,375 describe "page-interleaving" techniques wherein improved access times are achieved by accessing sequential memory pages which are interleaved between memory banks, such that accesses to bits in the same page as a previous access omit the row pre-charge cycle.
Additionally, as conventional electronic systems are increasingly designed according to board specifications which impose smaller physical constraints, there is less room being provided for components, such as DRAM chips. Thus, there is a need to define an approach for providing high-performance electronic storage in a physically more efficient manner.
One approach involves placing DRAM components in Single In-line Memory Modules (SIMMs). In this way, such SIMMs may be installed in banks to provide the total amount of memory desired. However, conventional interleaving techniques for accessing storage locations in SIMMs require a minimum of two banks, with memory expanding in increments of two banks. Thus, in systems where there is only enough space for two banks of memory, this requirement limits system designers from having an easy upgrade path to add more memory.
Instead, such designers need to remove all memory components from the system and replace such components with larger SIMMs to perform the desired upgrade. Because this approach leads to wasteful and expensive system memory upgrades, a better technique for digital storage is needed.
Another limitation of conventional interleave approaches for accessing digital memory from multiple storage banks is that separate address buses are used for each bank. In this way, at least one of the addresses in each bank changes at a different time in order to obtain the benefit of longer access time. Because this approach requires separate banks in increments of two, there is a need for an improved technique for accessing such digital memory.